Poseidon Design Systems
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Poseidonís technology significantly helps SoC designers in two fundamental areas:
  • Given a choice of processor cores and peripherals, it helps designers identify the most suitable combination for a specific end-use application.
  • It helps optimize the system performance by identifying hardware/ software bottlenecks and making the appropriate tradeoffs to resolve them.
SoC designers often have a choice of which processor cores and peripherals to use. To make the best design decisions during architectural exploration, they need to model the system using various components and co-simulate the hardware and software. Simulating SoC designs only at the RTL level has two problems:

  • RTL simulation is slow.
  • Both software and hardware performance are equally important in SoC design, and it is difficult to tune the performance of software at this lower level

Poseidon's technology allows designers to simulate processor-centric systems at higher levels of abstraction, including the instruction level and the cycle-accurate level. Poseidon's expertise in modeling and simulating processor-based systems ensures that software is given equal importance as hardware. During system simulation, both the software performance and hardware performance are investigated and the bottlenecks are identified for optimization.

Platform-based SoC designers often need to develop custom logic to enhance the processing power of the platform when it is otherwise not sufficient. To do this, they need to take the following steps:

  • Profile the software and identify the bottleneck functions.
  • Implement them in hardware (using custom logic).
  • Design an interface between the software and the custom logic.
  • Implement the interface in hardware.
  • Write device drivers for the software.
  • Make any necessary modifications in the software.
  • Integrate, test and debug.
Poseidon's automatic co-processor design solution is an ideal solution to this problem, because it eliminates all of these steps. Poseidon's technology can:
  • Profile the software at the instruction level, function level, and inner loop level and identify the bottlenecks at all levels.
  • Design custom instructions to implement these fixes.
  • Synthesize co-processor logic that implements the new instructions and is connected to the processor using a standard co-processor interface.
  • Generate tools -- compilers, debuggers, assemblers, etc. -- which are aware of this co-processor logic and the new custom instructions. For example, when the compiler encounters an inner loop for which a new instruction was designed, it incorporates the new instruction in the generated assembly code.
With this innovative new technology, SoC designers can get the benefits of the custom logic and accelerate their applications while shrinking their design cycle time.