Poseidon Design Systems
Hardware/ Software Partitioning Technology
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The high number of transistors available in today's SoCs means there is Triton Builderce for powerful custom logic in addition to processor cores, peripherals, and memory. The choice of what functions are to run on the processor as software, and what is to be partitioned off to run on custom hardware is a crucial one which has a profound impact on the product cost, performance, time-to-market, and scalability. Implementing computationally intensive parts of an application as custom hardware logic enables designers to overcome the limitations of instruction processors and extract the best performance from a system.

Today, partitioning of an application into hardware and software is a manual process. Engineers profile the application on the processor and find the bottleneck functions, which are then moved to hardware.

In addition to the problem of designing hardware/software interface and writing device drivers for controlling custom logic, there is a serious problem of scalability and extensibility of the device for future generations. There may be multiple versions of an essentially same algorithm, and a newer version of a standard may present yet another flavor of the same algorithm.

Moving each version of a function into hardware implies more work and extensibility problems in future generations. For example, a designer may move the motion compensation function in an MPEG decoder to hardware and release a SoC today, only to find a newer option of motion compensation defined in the next generation MPEG. The custom logic will then have to be redesigned.

At Poseidon, we realize the need to automate the process of hardware/software partitioning and add more intelligence to it. In addition to the function-level profiling of an application, it is necessary to profile at the instruction level and find recurring patterns of operation chains. In our MPEG example, different versions of the motion compensation algorithm may appear as different functions in C, but they may have similar inner loops that are computationally intensive. Thus it makes sense to move just these operations to hardware, rather than the whole function.

In addition, if the designers do not need to develop device drivers or modify software to run parts of the application on the hardware, it can reduce the design cycle time dramatically. With this in mind, Poseidon tools do the following:

  • Profile the application on a processor at the function level and the operation chain level and identify what should be moved into hardware.
  • Design the custom logic.
  • Generate tools - compiler, assembler, linker, simulator and debugger - that are aware of the custom logic, so that the right software image that uses the custom logic efficiently is generated without any changes to the application software code in C.
Thus the existence of the custom logic that speeds up the application is totally tranTriton Builderrent to the designer and handled completely by Poseidon tools. The same software can run on the bare processor as well as the processor with custom logic .

Poseidon's innovative approach to software-hardware partitioning shortens the design cycles dramatically, while ensuring scalability and extensibility for future generations of the SoC.